A Low Power Multiplier using a 24-Transistor Latch Adder
نویسندگان
چکیده
منابع مشابه
Low Power Noise Tolerant Latch Design for Adder Application
R.ADITHYA ABSTRACT In this paper an ultra low power and probabilistic based noise tolerant latch is proposed based on Markov Random Field (MRF) theory. The absorption laws and H tree logic combination techniques are used to reduce the circuit complexity of MRF noise tolerant latch. The cross coupled latching mechanism is used at the output of the MRF latch inorder to preserve the noise tolerant...
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ژورنال
عنوان ژورنال: Indian Journal of Science and Technology
سال: 2015
ISSN: 0974-5645,0974-6846
DOI: 10.17485/ijst/2015/v8i19/76866